The present invention relates to a technique for fabricating a semiconductor device, and particularly to a technique which is effective when applied to a semiconductor device including a metal insulator semiconductor field effect transistor (MISFET) of a generation of a gate length of 0.1 μm or less.
As a MISFET in which a short-channel effect is suppressed, a MISFET having two peaks in substrate dopant concentration distribution under a gate electrode is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 2002-198529.
FIG. 8 is a cross-sectional view illustrating a conventional MISFET, specifically a conventional p-MISFET having a gate length of 0.1 μm or less. The conventional MISFET shown in FIG. 8 is formed by the following method.
First, an n-well 2 is formed in a semiconductor substrate 1. Then, a first n-type doped layer 9 is formed in a surface of the n-well 2. A second n-type doped layer 10 is formed in a portion of the n-well 2 below the first n-type doped layer 9. The distribution of dopant concentration of the first n-type doped layer 9 in the depth direction has a first peak. The distribution of dopant concentration of the second n-type doped layer 10 in the depth direction has a second peak.
Next, a gate electrode 4 is formed over the semiconductor substrate 1 with a gate insulating film 3 interposed therebetween. Then, p-type source/drain extension regions 7 are formed in the semiconductor substrate 1 at both sides of the gate electrode 4.
Thereafter, insulating sidewall spacers having a multilayer structure of a silicon oxide film 5 and a silicon nitride film 6 are formed on the sides of the gate electrode 4, and then p-type source/drain doped regions 8 are formed in the semiconductor substrate 1 at both sides of the gate electrode 4.
The first n-type doped layer 9 and the second n-type doped layer 10 are formed to depths shallower than the junction depth of the source/drain doped regions 8. The first peak in the dopant concentration distribution of the first n-type doped layer 9 in the depth direction is located at a position deeper than a region in which channel is to be formed (hereinafter, referred to as a channel region) in the semiconductor substrate 1. The dopant concentration at the second peak in the dopant concentration distribution of the second n-type doped layer 10 is higher than that at the first peak in the dopant concentration distribution of the first n-type doped layer 9.
In the conventional MISFET structure described above, i.e., a MISFET structure which has two peaks: a first peak in the dopant concentration distribution of the first n-type doped layer 9 and a second peak in the dopant concentration distribution of the second n-type doped layer 10 and in which the dopant concentration at the second peak is higher than that at the first peak, the controllable width of a depletion layer is large, so that it is possible to reduce the subthreshold coefficient. This prevents decrease of the threshold voltage and, thereby, increases the switching speed of the MISFET. The foregoing description has been given on a p-MISFET but is also applicable to n-MISFETs.